SpaceX satellites are doing about 1000 collision avoidance maneuvers every single day. The addition of new networks is going to congest things even more and the risk of unavoidable cascading failure keeps increasing at a massive rate.
Those are pre-emptive moves for minimizing what is a very small chance of collisions, not narrowly escaped near certain collisions. Air traffic control does a similar thing with keeping planes spaced apart in zones under their control. In space a small thruster nudge will have a huge impact at a very low cost
That depends what you mean by "open ocean"? Vessels near ports or in defined traffic lanes frequently maneuver to avoid collisions as per the rules of the road. Outside territorial waters it's less common but still happens occasionally. Either way, those avoidance maneuvers are such routine events that no one really gathers data on them.
Loads of those result in crashes with some involving hundreds of cars.
Just one collision in space carries an ever-increasing risk of cascading into a major event with long-term effects (there's no a good way to call in a space wrecker to haul billions of tiny bits out of orbit).
Debris from a collision on water won't spread out into millions of floating pieces that speed around faster than a bullet, ripping random ships on the other side of the world to shreds.
> spread out into millions of floating pieces that speed around faster than a bullet, ripping random ships on the other side of the world to shreds
This isn't how debris clouds work. The most-complex ones occur when entirely separate orbits collide were you get an X-shaped (versus cylndricla or conic) debris cloud. But the energies of the collision inputs sharply curtail the orbits and places in said orbits the debris fragments can generally reach.
Idk, Iridium-Cosmos debris are still absolutely everywhere [0] after almost 20 years. The only place a ship collision's gonna leave debris is directly under it.
Space is big. Volume grows with radius in a way our intutiions don't seem to intuitively understand. Yes, debris in a space collision go further. But they're still bound by their energies. And that larger volume of collision debris (plus all other stuff in orbit minus the Moon) is still a smaller fraction of the orbital space than e.g. commercial air space on earth, and yes, that's including oceans.
Space is huge, but being on land has some advantages too. It's true that volume grows, but satellites don't have brakes in the way that cars do, nor is there a cleanup crew that removes the debris after a crash.
You can remove curbs and any other barrier to simulate the fact that cars can maneuver away from a crash site, but if no site is ever cleaned, and no car has meaningful brakes, crash sites are much scarier.
Water usage may be a drop in the bucket nationally, but they tend to put datacenters in areas without much water (often because evaporative cooling is less expensive in arid regions) and the effects to those local water supplies can be extreme.
I feel like I've been in a recession economy since the day I entered the workforce 14 years ago. The movement of the stock market has had no effect on my reality. It's like two different universes inhabited by two different sets of people.
IMO, all the narratives we were exposed to around privilege before and after COVID were a cover up of this fact that we have a two-class system which is explicitly creating this condition. The issue is at the system design level and goes far beyond "technology putting people out of a job". The privilege narrative was classic communist-style "accuse your enemy of what you're doing yourself." It was literally the privileged few preemptively accusing the unprivileged masses of being unfairly privileged in order to take control that narrative before it was used on them.
Rewriting critical stuff like hand-written SIMD takes a long time (though not as long as it took ARM because ARM had to overcome everything being written in just one ISA). Even a decade in, there are still lots of low-hanging fruit in RISC-V compilation that is still being dealt with. There's quite a few really great talks about the progress here and I think we're going to continue to see major gains in RISC-V performance via compiler changes for quite a while longer.
If such an instruction is so obviously important, we'll see it start popping up as a custom instruction in some cores then it will get adopted as an official extension by other companies trying to stay competitive.
> The problem is that RISC-V is never going to win at the high end. RISC-V will never have as much money driving it forward as x86 and ARM. As such, the blocks and integration will always lag.
Qualcomm recently bought Ventana and are looking at paying ARM billions (in addition to their current billions) for the privilege of designing their own cores. They sit on the RISC-V consortium and made proposals like Znew.
We could be seeing a high-performance RISC-V release from Qualcomm quite soon (especially if they can simply swap out the ARM decode for RISC-V).
Qualcomm beat ARM in court and reportedly pays 2-3% royalties where ARM was demanding 5-10% royalties.
Qualcomm's ARM license expires around 2028 with an option to extend to 2033 (for some amount of money). If Qualcomm is locked into ARM when renewal comes up, ARM is going to not only name the higher price, but likely charge even more to recover their lost revenue.
Qualcomm is already designing their own cores and ARM is charging them billions for the privilege. Increasing net profits 2-3% for simply doing the thing you are doing seems like a very easy choice. Increasing net profits 5-10% (maybe more) after the price hike seems like a fiduciary responsibility.
This isn't just talk either. Qualcomm already proposed a RISC-V Znew extension (nearly 300 pages of changes to make the ISA more like ARMv8). They bought Ventana (a company already done with their second very wide RISC-V design). They partnered with other companies to make Quintauris for promoting RISC-V too.
There's a non-zero chance we see a RISC-V design from Qualcomm before 2028 and I believe a near 100% certainty of a RISC-V design before 2033.
> I will make one ISA propsal: x86_64 should have had 32 instead of 16 registers
APX proposes exactly this along with 3-register syntax and some other things.
There are two big issues IMO.
1. It will take at least 15 years before most software ships with this because unlike something like AVX where you typically just rewrite a small part of your code that needs AVX, APX requires a 100% rewrite to take advantage.
2. APX instructions require an additional byte each time you use them compared to current instructions. I think there are still savings to be found, but they won't be as big as it might seem at first.
Lack of serious incentive combined with decades-long rollout seems a recipe for non-adoption at a time when RISC chips offer these features now.
reply